Teaching Computer Architecture through an Integrated Top-Down RISC-V Processor Design Approach

Abstract

Computer organization and architecture teaching has historically been supported by didactic simulators, notably associated with the MIPS architecture, whose simplicity favored the understanding of fundamental concepts. However, the rise of the RISC-V architecture, conceived as an open, modular, and extensible model, has reshaped the educational landscape, demanding new pedagogical approaches. Beyond being fundamental for the initial understanding of concepts such as pipelining, memory hierarchy, and instruction execution, simulation also provides a means to explore multiple abstraction levels and validate designs against a formal reference model. This dual role reinforces conceptual learning and fosters a more practical and applied educational experience. In this context, integration with simulation tools that provide support at multiple abstraction levels significantly enhances the exploration of fundamental aspects in the teaching–learning process of computer organization and architecture, while also assisting in the design of complex digital systems. This article presents a didactic–methodological approach that articulates different abstraction levels, ranging from functional and RTL simulation to validation and testing, considering a reference model integrated with the tools. Such an approach fosters interactive experimentation and customization of the RISC-V ISA and brings the teaching process closer to professional practice in computer engineering. A comparative analysis of existing simulators and a description of the proposed methodology highlight that combining simulations at different abstraction levels strengthens student training, offering a robust, modern, and contemporary learning ecosystem aligned with computing demands. Finally, the article discusses the results of applying this teaching approach during one semester of the Computer Engineering program at UFPE.