Implementation of a Branch Predictor in the 5-Stage MIPS Pipeline
DOI:
https://doi.org/10.5753/ijcae.2017.4862Abstract
Although branch prediction has a significant impact on processor performance, computer architecture textbooks do not provide details on its implementation. This work proposes a branch predictor for the 5-stage MIPS processor following the didactic sequence of the book “Computer Organization and Design” by Hennessy and Patterson. This paper presents the concept, modeling, case enumeration, and simplified implementation with the addition of just two units and some connections inserted into the data path of the 5-stage MIPS pipeline. The proposal serves as a basis to motivate the development of extensions and implementations of other predictors, as well as to reinforce concepts on the subject.
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