MIPSFPGA - An Incremental MIPS Simulator with FPGA Validation

Abstract

This paper presents innovations in teaching the MIPS processor architecture with the support of a graphical simulator. The proposed environment, named MIPSFPGA (Mips Incremental Processor Simulator and FPGA Prototyping), includes not only a graphical interface for visualizing the data path of various MIPS implementations with and without pipelines but also several additional features. First, the design can be graphically edited to explore other implementations. All projects from Patterson and Hennessy’s Computer Organization textbook are available. The design can be exported and prototyped on FPGA. Implementations can be debugged during simulation and prototyping. Finally, the methodology is incremental, allowing one to start with simple examples and progress to customizing and deriving new implementations and extensions.