Lessons Learned Using ArchC in Computer Architecture Laboratory
DOI:
https://doi.org/10.5753/ijcae.2016.4868Abstract
This paper presents a set of laboratory experiments based on the ArchC Architecture Description Language designed to fulfill the practical knowledge on Computer Architecture. These activities were designed over the last years and have been used in our discipline of Laboratory of Computer Architecture, where seventh semester students apply the knowledge they acquired in the theory classes. We present the experiments, covering 10 distinct topics in Computer Architecture, along with specific sections of the text-book to which they refer. We also show some of the experiences we acquired during the last years both on learning outcomes and student feedback.
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References
ArchC project website. [link].
MiBench embedded benchmark suite. [link].
SystemC project website. [link].
R. Azevedo, S. Rigo, and G. Araujo. Projeto e Desenvolvimento de Sistemas Embarcados Multiprocessados, pages 331–386. Ed. PUC-Rio, 2006.
R. Azevedo, S. Rigo, M. Bartholomeu, G. Araujo, C. Araujo, and E. Barros. The archc architecture description language and tools. Intl. J. Par. Program., 33(5), 2005.
L. Cai and D. Gajski. Transaction level modeling: an overview. In CODES+ISSS, 2003.
L. Duenha, G. Madalozzo, T. Santiago, F. Moraes, and R. Azevedo. Mpsocbench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies. J. of Parallel and Distributed Comp., 95, 2016.
J. Elder and M. D. Hill. Dinero IV trace-driven uniprocessor cache simulator. [link], 2003.
M. Garcia, R. Azevedo, and S. Rigo. Optimizing simulation in multiprocessor platforms using dynamic-compiled simulation. In WSCAD-SSC, pages 80–87, 2012.
M. Guedes, R. Auler, E. Borin, and R. Azevedo. An ArchC approach for automatic energy consumption characterization of processors. In RSP, pages 57–63, 2012.
J. L. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 5th ed., 2011.
Joint Task Force on Computing Curricula, ACM and IEEE. Curriculum Guidelines for Undergraduate Degree Pro- grams in Computer Science. ACM, 2013.
F. Kronbauer, A. Baldassin, B. Albertini, P. Centoducatte, S. Rigo, G. Araujo, and R. Azevedo. A flexible platform framework for rapid transactional memory systems prototyping and evaluation. In RSP ’07, pages 123–129, 2007.
B. Nichols, D. Buttlar, and J. P. Farrell. Pthreads Programming. O’Reilly, 1996.
D. Patterson and J. L. Hennessy. Computer Organization & Design: The Hardware/Software Interface. 5th ed., 2013.
S. Rigo, R. Azevedo, P. Centoducatte, and G. Araujo. Uma nova abordagem para um curso de projeto de sistemas computacionais. In WEAC, 2006.
S. Rigo, R. Azevedo, and L. Santos. Electronic system level design: An open-source approach, 2011.
S. Rigo, M. Juliato, R. Azevedo, G. Araujo, and P. Centoducatte. Teaching computer architecture using an architecture description language. In Proc. workshop on Comp. architecture education (WCAE). ACM, 2004.
N. Ventroux, A. Guerre, T. Sassolas, L. Moutaoukil, G. Blanc, C. Bechara, and R. David. SESAM: An MPSoC simulation environment for dynamic application processing. In Intl. Conf. on Comp. and Information Technology, 2010.
P. Viana, E. Barros, S. Rigo, R. Azevedo, and G. Araujo. Modeling and simulating memory hierarchies in a platformbased design methodology. In DATE ’04, page 10734, 2004.
H. Wagstaff, M. Gould, B. Franke, and N. Topham. Early partial evaluation in a jit-compiled, retargetable instruction set simulator generated from a high-level architecture description. In DAC, May 2013.
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