Utilização dos simuladores do MPSoCBench para o ensino e aprendizagem de Arquitetura de Computadores
DOI:
https://doi.org/10.5753/ijcae.2016.4872Abstract
Este artigo propõe uma metodologia de ensino complementar às disciplinas de Arquitetura de Computadores fundamentada em projetos de exploração arquitetural, experimentação e análise de resultados. Adotou-se o MPSoCBench como ferramenta de simulação, o qual possui modelos funcionais de sistemas multiprocessados e fornece estimativas de desempenho, temporização e consumo de potência para principais unidades funcionais dos sistemas computacionais.
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Referências
OSCI TLM-2.0 Language Reference Manual. Software version: TLM 2.0.1 Document version: JA32. [link].
IEEE Std 1666TM Standard SystemC Language Reference Manual. IEEE Computer Society, January 2012.
Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano Araujo, and Edna Barros. The ArchC Architecture Description Language and Tools. In International Journal of Parallel Programming. Vol. 33, No. 5, pages 453–484. October 2005.
Liana Duenha, Guilherme Madalozzo, Thiago Santiago, Fernando Moraes, and Rodolfo Azevedo. Mpsocbench: a benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies. In Journal of Parallel and Distributed Computing, volume 95, pages 138–157. Elsevier, June 2016.
Marcelo Guedes, Rafael Auler, Liana Duenha, Edson Borin, and Rodolfo Azevedo. An automatic energy consumption characterization of processors using archc. Journal of Systems Architecture, 59(8):603 – 614, 2013.
S.M.Z. Iqbal, Yuchen Liang, and H. Grahn. Parmibench - an open-source benchmark for embedded multiprocessor systems. Computer Architecture Letters, 9(2):45–48, Feb 2010.
Sheng Li, JH Ahn, and RD Strong. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 42nd Annual International Symposium on Microarchitecture, pages 469–480, 2009.
Fernando Moraes, Ney Calazans, Aline Mello, Leandro Möller, and Luciano Ost. Hermes: an infrastructure for low area overhead packet-switching networks on chip. volume 38, pages 69–93. Elsevier Science Publishers B. V., Amsterdam, The Netherlands, The Netherlands, October 2004.
P. Rosenfeld, E. Cooper-Balis, and B. Jacob. Dramsim2: A cycle accurate memory system simulator. In IEEE-Computer Architecture Letters, ISSN 1556-6056, pages 16–19, Maryland, USA, June 2011. IEEE.
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The Splash-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture - ISCA’95, pages 24–36. ACM, 1995.
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Este trabalho está licenciado sob uma licença Creative Commons Attribution 4.0 International License.
