Computer Architecture under Energy Consumption Vision

Authors

  • Edward David Moreno UFS
  • Franklin M. R. Junior UFS
  • Felipe dos Anjos Lima UFS
  • Wanderson Roger A. Dias IFS

DOI:

https://doi.org/10.5753/ijcae.2013.4942

Keywords:

embedded systems, benchmarks, compiler optimizations, energy and power consumption

Abstract

This paper presents a new methodology for teaching computer architecture under energy consumption vision. The educational goals of this methodology are fivefold, know and understand the integration about: (i) computer architecture of traditional platforms (for example SPARC, MIPS) (ii) computer architecture of embedded systems (ARM) (iii) modern and popular applications (embedded systems), (iv) optimizations from compilers and (v) there is a synergy among of them for performance and energy consumption point of view.

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Referências

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W. R. A. Dias, E. D. Moreno, and R. S. Barreto, "Architectural Characterization and Code Compression in Embedded Processors". IEEE Latin America Transactions, 10(4):1865-1873, June 2012.

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Published

2013-12-01

Como Citar

Moreno, E. D., R. Junior, F. M., Lima, F. dos A., & Dias, W. R. A. (2013). Computer Architecture under Energy Consumption Vision. International Journal of Computer Architecture Education, 2(1), 5–8. https://doi.org/10.5753/ijcae.2013.4942

Issue

Vol. 2 No. 1 (2013)

Section

Artigos Completos

Licença

Copyright (c) 2013 Os autores

Creative Commons License
Este trabalho está licenciado sob uma licença Creative Commons Attribution 4.0 International License.