An Analysis of Network-on-Chip Tools and Their Features for Use in Teaching
DOI:
https://doi.org/10.5753/ijcae.2015.4929Keywords:
Networks-on-Chip, Tools, TeachingAbstract
Networks-on-Chip (NoCs) were proposed as a solution for the interconnection of cores in high-density integrated systems. These networks are already used by the industry, which will result in a demand for human resources trained to handle this technology. Teaching concepts about NoCs needs to be supported by tools that allow students to explore their design space, with various tools available that can provide this capability. However, to facilitate the use of these tools in teaching, it is important that they offer additional support features beyond those needed for use in research activities. In this sense, this work presents an analysis of NoC tools described in the literature and identifies which teaching-support features are most commonly offered. It also identifies which tools provide the highest number of these features, as well as highlights gaps to be filled to facilitate and accelerate the adoption of these tools with a view to improving the teaching and learning process about NoCs.
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