Uma Análise sobre Ferramentas de Redes-em-Chip e seus Recursos para Uso no Ensino
DOI:
https://doi.org/10.5753/ijcae.2015.4929Keywords:
Redes-em-Chip, Ferramentas, EnsinoAbstract
As Redes-em-Chip (do inglês, NoCs – Networkson- Chip) foram propostas como solução para interconexão de núcleos em sistemas integrados de alta densidade. Essas redes já são utilizadas pela indústria e isso irá resultar em uma demanda pela formação de recursos humanos aptos a lidar com essa tecnologia. O ensino de conceitos sobre NoCs precisa ser apoiado por ferramentas que permitam ao estudante explorar o seu espaço de projeto, sendo que existem diversas ferramentas com tal capacidade. Porém, para facilitar o uso dessas ferramentas no ensino, é importante que estas ofereçam recursos de apoio adicionais aos necessários para o uso em atividades de pesquisa. Neste sentido, este trabalho apresenta uma análise sobre ferramentas de NoC descritas na literatura e identifica quais recursos úteis para o ensino que são mais comumente oferecidos. Também identifica quais ferramentas oferecem maior quantidade desses recursos, assim como evidencia lacunas a serem preenchidas para facilitar e acelerar a adoção dessas ferramentas com vistas à melhoria do processo de ensino e aprendizagem sobre NoCs.
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C. A. Zeferino, “Redes-em-Chip: Arquiteturas e modelos para avaliação de área e desempenho,” Tese de Doutorado, Universidade Federal do Rio Grande do Sul, 2003.
A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg e D. Lindqvist, “Network on chip: An architecture for billion transistor era,” In Proc. of the IEEE NorChip Conf., vol. 31. 2000.
P. Guerrier e A. Greiner, “A generic architecture for on-chip packetswitched interconnections,” Proc. of the Conf. on Design, Automation and Test in Europe. ACM, 2000.
T. Bjerregaard e S. Mahadevan, “A survey of research and practices of Network-on-Chip,” ACM Computing Surveys (CSUR) 38.1 (2006): 1.
A. Agarwal, C. Iskander e R. Shankar, “Survey of network on chip (noc) architectures and contributions,” J. of Engineering, Computing and Architecture, vol. 3, n. 1, 2009, p. 21-27.
L. Benini e G. De Micheli. Networks on chips: technology and tools. Academic Press, 2006.
A. B. Achballah e S. B. Saoud, “A survey of network-on-chip tools,” Int. J. of Advanced Computer Science and Applications. vol. 4, n. 9, p. 61-67, 2013.
EZchip. TILE-Gx72 Processor: Product Brief. 2013.
M. Gries, U. Hoffmann, M. Konow e M. Riepen, “SCC: A Flexible Architecture for Many-Core Platform Research,” in Computing Science Engineering, vol. 13, n. 6, 2011, p. 79-83.
J.-J. Lecler e G. Baillieu, “Application driven network-on-chip architecture exploration & refinement for a complex SoC,” Design Automation for Embedded Systems, vol. 15, n. 2, p. 133-158, 2011.
The Network Simulator - ns-2. Disponível em: [link]
M. Ali, M. Welzl, A. Adnan e F. Nadeem, “Using the Ns-2 network simulator for evaluating network on chips (NoC),” In Emerging Technologies, 2006. ICET'06. Int. Conf. on, p. 506-512. IEEE, 2006.
Noxim: Network on Chip Simulator, 2015. Disponível em: [link].
K. Swaminathan, D. Thakyal, S. G. Nambiar, G. Lakshminarayanan e S. Ko, “Enhanced Noxim simulator for performance evaluation of network on chip topologies,” In Engineering and Computational Sciences (RAECS), 2014 Recent Advances in, p. 1-5. IEEE, 2014.
NIRGAM: a Simulator for NoC Interconnect Routin Applocation Modeling. Disponível em: [link].
N. Choudhary, M. S. Gaur e V. Laxmi, “Irregular NoC Simulation Framework: IrNIRGAM,” In Int. Conf. on Emerging Trends in Networks and Computer Communications (ETNCC). 2011, p. 1-5. IEEE, 2011.
M. Lis, K. S. Shim, M. H. Cho, P. Ren, O. Khan e S. Devadas, “DARSIM: a parallel cycle-level NoC simulator,” In MoBS 2010-Sixth Annual Wksp. on Modeling, Benchmarking and Simulation. 2010.
P. Ren, M. Lis, M. H. Cho, K. S. Shim e C. W. Fletcher, “HORNET: A Cycle-Level Multicore Simulator,” In IEEE Transactions on Computeraided design of integrated circuits and systems. vol. 31, n. 6, 2012, p. 890-903.
HORNET, 2011. Disponível em: [link].
C. Seiculescu, S. Murali, L. Benini, e G.D. Micheli, "SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips", J. IEEE Trans. on CAD of Integrated Circuits and Systems, 2010, p.1987-2000.
A. B. Kahng, B. Li, L. Peh e K. Samadi, “Orion 2.0: A power-area simulator for interconnection networks,” In IEEE Transactions on Very Large Scale Integration (VLSI) systems, 2012, p. 191-196.
Orion: A Power-Performance Simulator for Interconnection Networks, 2012. Disponível em: [link].
S. Murali e G. De Micheli, “SUNMAP: a tool for automatic topology selection and generation for NoCs,” In Proc. of the 41st annual Design Automation Conf., ACM, 2004. p. 914-919.
J. Chan, S. Parameswaran, “NoCGEN: a template based reuse methodology for Networks-on-Chip architecture,” In Proc. of 17th Int. Conf. on VLSI Design, 2004, p. 717-720.
N. Jiang, D. U. Becker, G. Michelogiannakis, J. Balfour, B. Towles, J. Kim e W. J. Dally, “A Detailed and Flexible Cycle-Accurate Networkon-Chip Simulator,” In Proc. of the 2013 IEEE Int. Symp. on Performance Analysis of Systems and Software, 2013.
BookSim Interconnection Network Simulator. Disponível em: [link].
E. A. Carara, R. P. de Oliveira, N. L. V. Calazans, F. G. Moraes, “HeMPS – A Framework for NoC-Based MPSoC Generation,” In IEEE Int. Symp. on Circuits and Systems (ISCAS), 2009. p. 1345-1348.
HeMPS, 2011. Disponível em: [link].
L. Möller, L. S. Indrusiak e M. Glesner, “NoCScope: A graphical interface to improve Networks-on-Chip monitoring and design space exploration," In 4th Int.Design and Test Wksp. (IDT), 2009. p.1-6.
P. Gottschling, H. Ying e K. Hofmann, “GSNOC UI – A Comfortable Graphical User Interface for Advanced Design and Evaluation of 3-Dimensional Scalable Networks-on-Chip,” In Int. Conf. on High Performance Computing and Simulation (HPCS), 2012. p. 261-267.
H. Ying, A. Jaiswal, M. A Abd El Ghany, T. Hollstein, and K. Hofmann, “A Simulation Framework for 3-Dimension Networks-on-Chip with Different Vertical Channel Density Configurations,” IEEE DDECS, Estonia, 2012.
H. Hossain, M. Ahmed, A. Al-Nayeem, T. Z. Islam e M. M. Akbar, “Gpnocsim - A General Purpose Simulator for Network-On-Chip," In Int. Conf. on Information and Communication Technology, 2007. ICICT '07, 2007. p.254-257.
gpNoCSim++, 2013. Disponível em: [link].
N. Binkert et al., “The gem5 simulator,” in ACM SIGARCH Computer Architecture News, vol. 39, n. 2, 2011. p. 1-7.
The gem5 Simulator, 2015. Disponível em: [link].
P. Abad, P. Prieto, L. G. Menezo, A. Colaso, V. Puente e J.-A. Gregorio, “TOPAZ: Na Open-Source Interconnection Network Simulator for chip Multiprocessors and Supercomputers,” In Sixth IEEE/ACM Int. Symp. on Networks-on-Chip, 2012. p. 99-106.
TOPAZ, 2015. Disponível em: [link].
Y. Ben-Itzhak, E. Zahavi, I. Cidon e A. Kolodny, “HNOCS: Modular open-source simulator for Heterogeneous NoCs,” In Int. Conf. on Embedded Computer Systems (SAMOS), 2012. p. 51-57.
OMNet++: Discrete Event Simulator, 2015. Disponível em: [link].
HNoCS: Modular Open-Source Simulator for Heterogeneous NoCs, Disponível em: [link].
L. Guang, E. Nigussie, J. Plosila, J. Isoaho e H. Tenhunen, “HLSDoNoC: High-Level Simulator for Dynamically Organizational NoCs,” In IEEE 15th Int. Design and Diagnostics of Eletronic Circuits & Systems (DDECS), 2012. p. 89-94.
J. H. Ahn, S. Li, S. O e N. P. Jouppi, “McSimA+: A Manycore Simulator with Application-level+ Simulation and Detailed Microarchitecture Modeling,” In IEEE Int. Symp. on Performance Analysis of Systems and Software (ISPASS), 2013, p. 74-85.
McSimA+, 2014. Disponível em [link].
S. D. Ponpandi, Z. Zhang e A. Tyagi, “PolyNOC – A Polymorphic thread simulator for NOC communication based embedded systems,” In Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig), 2013. p. 1-8.
D. Ghosh, P. Ghosal e S. P. Mohanty, “A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures,” In Int. Conf. on Information Technology (ICIT), 2014. p. 311-315.
T.-S. Hsu, J.-L. Chiu, C.-K. Yu e J.-J. Liou, “A Fast and Accurate Network-on-Chip Timing Simulator with a Flit Propagation Model,” In 20th Asia and South Pacific Design Automation Conf. (ASP-DAC), 2015, p. 797-802.
C. A. Zeferino, J. V. Bruch e M. R. Pizzoni, “BrownPepper: a SystemCbased Simulator for Performance Evaluation of Networks-on-Chip,” In 17th Int. Conf. On Very Large Scale Integration (VLSI-SOC), 2009. p. 223-226.
E. A. Silva, “RedScarf: ambiente para avaliação de desempenho de Rede-em-Chip,” Trabalho Técnico Científico de Conclusão de Curso, Universidade do Vale do Itajaí, 2014.
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