A Double-Phase Evolvable Hardware Architecture Learning Platform: Design, Simulation, and Prototyping Testbed

Authors

  • Bernardo Guerra Pereira Cunha PUC Minas
  • Flávia Magalhães Freitas Ferreira PUC Minas
  • Carlos Augusto Paiva da Silva Martins PUC Minas

DOI:

https://doi.org/10.5753/ijcae.2022.4835

Abstract

The world is changing. Scientists and engineers create solutions for daily problems every day. Time is a crucial factor in many contexts, for example, academia. Undergraduate, master, or doctorate tasks in engineering and computer science tend to use enhanced methods that are computationally expensive for regular computers. It is the case of Hardware development. When a research issue deals with complex and multidisciplinary topics, like Evolvable Hardware, things become even worse. In this case, students and researchers spend a huge amount of time prototyping and making experiments in traditional EDA tools. This work shows the initial results of a double-phase evolvable hardware design learning platform, a combination of a computational interface for logic simulation and hardware prototyping.

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Published

2022-12-01

How to Cite

Cunha, B. G. P., Ferreira, F. M. F., & Martins, C. A. P. da S. (2022). A Double-Phase Evolvable Hardware Architecture Learning Platform: Design, Simulation, and Prototyping Testbed. International Journal of Computer Architecture Education, 11(1), 15–22. https://doi.org/10.5753/ijcae.2022.4835

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