Evaluation of branch predictors through simulators as part of the teaching and learning process of Computer Architecture
DOI:
https://doi.org/10.5753/ijcae.2017.4860Abstract
This paper presents the results of applying functional processor simulators as an additional educational resource for teaching computer architecture. Specifically, the paper demonstrates the use of simulators for evaluating branch predictors as part of an auxiliary methodology during the teaching of this topic in the Computer Architecture course. The methodology involves using execution traces of a set of applications generated by simulators of four processor models and, from these, characterizing and evaluating the performance of eight branch predictors.
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