Teaching Vector Architectures Using a MIPS Instruction Simulator
DOI:
https://doi.org/10.5753/ijcae.2015.4923Keywords:
Vector Processors, MIPS Simulator, Teaching Computer ArchitectureAbstract
Vector processors, along with the MIPS processor, constitute two important milestones in the development and teaching of computer architecture. In recent decades, several extensions of the MIPS instruction set have been specified, including a SIMD extension in 2014. This article presents the first vector simulator based on MIPS to be used in computer architecture classes in Computer Science and Engineering courses. The proposed implementation is based on MARS, an open-source MIPS32 simulator. The proposed simulator is called Vector MARS or VMARS and features a robust and intuitive interface that assists in the simulation of MIPS vector instructions while also supporting the standard MIPS32 instruction set. Along with the VMARS simulator, examples are provided to illustrate the use of vector instructions available in the MIPS extension.
Downloads
References
D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3rd ed. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2007.
J. L. Hennessy and D. A. Patterson, Computer Architecture, Fifth Edition: A Quantitative Approach, 5th ed. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2011.
R. S. Ferreira, A. C. S. Beck, L. Carro, A. Toledo, and A. Silva, “A java framework to teach computer architecture,” in New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design. Springer, 2005, pp. 25–35.
R. Ferreira, J. Nacif, S. Magalhaes, T. Almeida, and R. Pacifico, “Be a simulator developer and go beyond in computing engineering,” in Frontiers in Education Conference (FIE), 2015 IEEE, Oct 2015, pp. 1–8.
J. R. Larus, “Spim: A mips32 simulator,” 1990–2010, [link] (Visited on April 15, 2015).
K. Meinz, “Webmipsasm v2.1,” 2015, [link] (Visited on April 15, 2015).
T.Pittman, “Tinymips (machine instruction processing simulator),” 2003, [link] (Visited on April 15, 2015).
D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, and V. Catania, “Supporting undergraduate computer architecture students using a visual mips64 cpu simulator,” Education, IEEE Transactions on, vol. 55, no. 3, pp. 406–411, Aug 2012.
K. Vollmar and P. Sanderson, “Mars: An education-oriented mips assembly language simulator,” SIGCSE Bull., vol. 38, no. 1, pp. 239– 243, Mar. 2006.
G. Fontes and R. Ferreira, “Ensino de organizacoes de memoria em arquiteturas paralelas usando placas graficas aceleradores,” International Journal of Computer Architecture Education (IJCAE), vol. 2, no. 1, 2013.
I. Technologies., MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module, 1st ed. 955 East Arques Avenue, Sunnyvale, CA 94085-4521: MIPS Technologies Inc., 2014.
“IEEE Standard for Floating-Point Arithmetic,” Microprocessor Standards Committee of the IEEE Computer Society, 3 Park Avenue, New York, NY 10016-5997, USA, Tech. Rep., Aug. 2008.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2015 Os autores
This work is licensed under a Creative Commons Attribution 4.0 International License.
