Multi-Core Processor Programming: An Educational Experience Using FPGA Embedded Didactic Platforms
DOI:
https://doi.org/10.5753/ijcae.2014.4934Keywords:
multi-core, teaching, parallel programming, simulatable platformsAbstract
The popularization of multi-core architectures has imposed the need for modifications in the teaching methods of computer architecture courses. The availability of simulable architectural models, described both with high-level languages and hardware description languages, raises the effectiveness level of the teaching process. This article describes teaching experiences carried out at the Federal University of Piauí, based on the development and use of simulable architectural models. These experiences showed that the success rate in performing tasks associated with multi-core programming increased from 63% to 87% of the involved students.
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Zhongwen Li; Wuling Lv, "Research on Curriculum Design of “Realtime Analysis and Design” Based on Multi-core Platform,"Young Computer Scientists, 2008. ICYCS 2008. The 9th International Conference for, vol., no., pp.2572,2576, 18-21 Nov. 2008
Jianhua Li; Weibin Guo; Hong Zheng, "An Undergraduate Parallel and Distributed Computing Course in Multi-Core Era,"Young Computer Scientists, 2008. ICYCS 2008. The 9th International Conference for , vol., no., pp.2412,2416, 18-21 Nov. 2008
Manogaran, E., "ACt-PBL: An Adaptive Approach to Teach Multi-core Computing in University Education," Technology for Education (T4E), 2013 IEEE Fifth International Conference on, vol., no., pp.19,23, 18-20 Dec. 2013
Udugama, L.S.K.; Geeganage, J.; Kuruppuarachchi, W.V., "A configurable multi-core processor for teaching parallel processing,"Industrial and Information Systems (ICIIS), 2013 8th IEEE International Conference on, vol., no., pp.326,331, 17-20 Dec. 2013
Jianfeng Yang; Yinbo Xie; Qing Geng; Jolly Wang; Bao, N., "Using cP2BL in Teaching Multi-Core Related Contents," Young Computer Scientists, 2008. ICYCS 2008. The 9th International Conference for , vol., no., pp.2449,2453, 18-21 Nov. 2008
Hamblen, J. O.; Hall, T. S.; Furman, M. D.; Rapid Prototyping od Digital Systems – Quartuss II Edition. Springer. 2006.
A. Junqueira and A. Suzim. Microprocessador RISC CMOS de 32 bits. Master's thesis, Universidade Federal do Rio Grande do Sul, 1993
Silva, I. S.; Nepomuceno, R.; Mafuta, T.; Carvalho, E.S., "uVMP: Virtualizable multi-core platform,"Informatica (CLEI), 2012 XXXVIII Conferencia Latinoamericana En, vol., no., pp.1,6, 1-5 Oct. 2012
Luz, L. O.; Silva, I. S.; Soares, T. R. B. S.; MaRISCO - A Multi-Core Platform. In: SFORUM-Student Forum on Microeletronics, 2012, Brasília. Anais - SBCCI Symposium on Itegrated Circuits and Systems Design, 2012.
Vilela, G.; Correa, E.; Kreutz, M., "A LLVM Based Development Environment for Embedded Systems Software Targeting the RISCO Processor," Computing System Engineering (SBESC), 2012 Brazilian Symposium on, vol., no., pp.77,82, 5-7 Nov. 2012.
Fernandes, S. R.; Oliveira, B. C.; Costa, M.; Silva, I. S., "Processing while routing: a network-on-chipbased parallel system,"Computers & Digital Techniques, IET, vol.3, no.5, pp.525,538, September 2009.
Silva, F. C.; Silva, I. S.; Luz, L. O.; Nepomuceno, R., “Designing a Complete Pipelined Datapath to MIPS ISA: Learning in Pratice”. In: SFORUM-Student Forum on Microeletronics, 2014, Aracaju. Anais - SBCCI Symposium on Itegrated Circuits and Systems Design, 2014. Accepted Paper.
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